Preface
Acknowledgment
List of Abbreviations
List of Figures
List of Tables
1 INTRODUCTION
1. High-Frequency Integrated Analog Filtering
2. Multirate Switched-Capacitor Circuit Techniques
3. Sampled-Data Interpolation Techniques
4. Research Goals and Design Challenges
2 IMPROVED MULTIRATE POLYPHASE-BASED INTERPOLATION STRUCTURES
1. Introduction
2. Conventional and Improved Analog Interpolation
3. Polyphase Structures for Optimum-class Improved Analog Interpolation
4. Multirate ADB Polyphase Structures
4.1 Canonic and Non-Canonic ADB Realizations
4.1.1 FIR System Response
4.1.2 IIR System Response
4.2 SC Circuit Architectures
5. Low-Sensitivity Multirate IIR Structures
5.1 Mixed Cascade/Parallel Form
5.2 Extra-Ripple IIR Form
6. Summary
3 PRACTICAL MULTIRATE SC CIRCUIT DESIGN CONSIDERATIONS
1. Introduction
2. Power Consumption Analysis
3. Capacitor-Ratio Sensitivity Analysis
3.1 FIR Structure
3.2 IIR Structure
4. Finite Gain & Bandwidth Effects
5. Input-Referred Offset Effects
6. Phase Timing-Mismatch Effects
6.1 Periodic Fixed Timing-Skew Effect
6.2 Random Timing-Jitter Effects
7. Noise Analysis
8. Summary
4 GAIN- AND OFFSET- COMPENSATION FOR MULTIRATE SC CIRCUITS
1. Introduction
2. Autozeroing and Correlated-Double Sampling Techniques
3. AZ and CDS SC Delay Blocks with Mismatch-Free Property
3.1 SC Delay Block Architectures
3.2 Gain and Offset Errors - Expressions and Simulation Verification
3.3 Multi-Unit Delay Implementations
4. AZ and CDS SC Accumulators
4.1 SC Accumulator Architectures
4.2 Gain and Offset Errors - Expressions and Simulation Verification
5. Design Examples
6. Speed and Power Considerations
7. Summary
5 DESIGN OF A 108 MHZ MULTISTAGE SC VIDEO INTERPOLATING FILTER
1. Introduction
2. Optimum Architecture Design
2.1 Multistage Polyphase Structure with Half-Band Filtering
2.2 Spread-Reduction Scheme
2.3 Coefficient-Sharing Techniques
3. Circuit Design
3.1 l(st)-Stage
3.2 2(nd)-and 3(rd)-Stage
3.3 Digital Clock Phase Generation
4. Circuit Layout
5. Simulation Results
5.1 Behavioral Simulations
5.2 Circuit-Level Simulations
6. Summary
6 DESIGN OF A 320 MHz FREQUENCY-TRANSLATED SC BANDPASSINTERPOLATING FILTER
1. Introduction
2. Prototype System-Level Design
2.1 Multi-notch FIR Transfer Function
2.2 Time-Interleaved Serial ADB Polyphase Structure withAutozeroing
3. Prototype Circuit-Level Design
3.1 Autozeroing ADB and Accumulator
3.2 High-Speed Multiplexer
3.3 Overall SC Circuit Architecture
3.4 Telescopic opamp with Wide-Swing Biasing
3.5 nMOS Switches
3.6 Noise Calculation
3.7 I/0 Circuitry
3.8 Low Timing-Skew Clock Generation
4. Layout Considerations
4.1 Device and Path Matching
4.2 Substrate and Supply Noise Decoupling
4.3 Shielding
4.4 Floor Plan
5. Simulation Results
5.1 Opamp Simulations
5.2 Filter Behavioral Simulations
5.3 Filter Transistor-Level and Post-Layout Simulations
6. Summary
7 EXPERIMENTAL RESULTS
1. Introduction
2. PCB Design
2.1 Floor Plan
2.2 Power Supplies and Decoupling
2.3 Biasing Currents
2.4 Input and Output Network
3. Measurement Setup and Results
3.1 Frequency Response
3.2 Time-Domain Signal Waveforms
3.3 One-Tone Signal Spectrum
3.4 Two-Tone Intermodulation Distortion
3.5 THD and IM3 vs. Input Signal Level
3.6 Noise Performance
3.7 CMRR and PSRR
4. Summary
8 CONCLUSIONS
APPENDIX 1 TIMING-MISMATCH ERRORS WITH NONUNIFORMLY HOLDING EFFECTS
1. Spectrum Expressions for IU-ON(SH)and IN-CON(SH)
1.1 IU-ON(SH)
1.2 IN-CON(SH)
2. Closed Form SINAD Expression for IU-ON(SH)and IN- CON(SH)
2.1 IU-ON(SH)
2.2 IN-CON(SH)
3. Closed Form SFDR Expression for IN-CON(SH)systems
4. Spectrum Correlation of IN-OU(IS)and IU-ON(SH)
APPENDIX 2 NOISE ANALYSIS FOR SC ADB DELAY LINE AND POLYPHASE SUBFILTERS
1. Output Noise of ADB Delay Line
2. Output Noise of Polyphase Subfilters
2.1 Using TSI Input Coefficient SC Branches
2.2 Using OFR Input Coefficient SC Branches
APPENDIX 3 GAIN, PHASE AND OFFSET ERRORS FOR GOC MF SC DELAY CIRCUIT I AND J
1. GOC MF SC Delay Circuit I
2. GOC MF SC Delay Circuit J |
